? semiconductor components industries, llc, 2005 january, 2005 ? rev. 2 1 publication order number: 74FST3125/d 74FST3125 4-bit bus switch the on semiconductor 74FST3125 is a quad, high performance switch. the device is cmos ttl compatible when operating between 4 and 5.5 volts. the device exhibits extremely low r on and adds nearly zero propagation delay. the device adds no noise or ground bounce to the system. the device consists of four independent 1?bit switches with separate output/enable (oe ) pins. port a is connected to port b when oe is low. if oe is high, the switch is high z. features ? r on 4 typical ? less than 0.25 ns?max delay through switch ? nearly zero standby current ? no circuit bounce ? control inputs are ttl/cmos compatible ? pin?for?pin compatible with qs3125, fst3125, cbt3125 ? all popular packages: qsop?16, tssop?14, soic?14 ? all devices in package tssop are inherently pb?free* oe 1 oe 2 gnd 2b 2a 1b 1a v cc 4b 3b 3a oe 3 4a oe 4 nc 1b 2b 2a oe 2 1a oe 1 v cc 4b 3b 3a oe 3 4a oe 4 gnd nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 2 3 4 5 6 7 16 15 14 13 12 11 10 89 figure 1. pin assignment for soic and tssop figure 2. pin assignment for qsop *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. description pin names oe 1 , oe 2 , oe 3 , oe 4 1a, 2a, 3a, 4a a = assembly location l, wl = wafer lot y = year w, ww = work week tssop?14 dt suffix case 948g 14 1 qsop?16 qs suffix case 492 soic?14 d suffix case 751a 14 1 fst 3125 alyw fst3125 awlyww 14 1 marking diagrams s3125 alyw 16 1 pin bus switch enables bus a 1b, 2b, 3b, 4b bus b nc not connected 16 1 see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1 14 http://onsemi.com
74FST3125 http://onsemi.com 2 2 1 5 4 9 10 12 13 3 6 8 11 1b 2b 3b 4b 1a 2a 3a 4a oe 1 oe 2 oe 3 oe 4 figure 3. logic diagram truth table inputs outputs oe a, b l a = b h z ordering information device order n mber package shipping 2 device order number package shipping 2 74FST3125d soic?14 55 units / rail 74FST3125dr2 soic?14 2500 units / tape & reel 74FST3125dt tssop* (pb?free) 96 units / rail 74FST3125dtr2 tssop* (pb?free) 2500 units / tape & reel 74FST3125qs qsop?16 96 units / rail 74FST3125qsr qsop?16 2500 units / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb?free.
74FST3125 http://onsemi.com 3 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to 7.0 v v o dc output voltage 0.5 to 7.0 v i ik dc input diode current v i gnd 50 ma i ok dc output diode current v o gnd 50 ma i o dc output sink current 128 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 1) soic tssop qsop 125 170 200 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) 2000 200 v i latchup latchup performance above v cc and below gnd at 85 c (note 4) 500 ma maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. measured with minimum pad spacing on an fr4 board, using 10 mm?by?1 inch, 2?ounce copper trace with no air flow. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc supply voltage operating, data retention only 4.0 5.5 v v i input voltage (note ) 0 5.5 v v o output voltage (high or low state) 0 v cc v t a operating free?air temperature 40 85 c t/ v input transition rise or fall rate switch control input switch i/o 0 0 5 dc ns/v 5. unused control inputs may not be left open. all control inputs must be tied to a high? or low?logic input voltage level.
74FST3125 http://onsemi.com 4 dc electrical characteristics v cc t a = 40 c to 85 c symbol parameter conditions (v) min typ* max unit v ik clamp diode resistance i in = 18ma 4.5 1.2 v v ih high?level input voltage 4.0 to 5.5 2.0 v v il low?level input voltage 4.0 to 5.5 0.8 v i i input leakage current 0 v in 5.5 v 5.5 1.0 a i oz off?state leakage current 0 a, b v cc 5.5 1.0 a r on switch on resistance (note 6) v in = 0 v, i in = 64 ma 4.5 4 7 v in = 0 v, i in = 30 ma 4.5 4 7 v in = 2.4 v, i in = 15 ma 4.5 8 15 v in = 2.4 v, i in = 15 ma 4.0 11 20 i cc quiescent supply current v in = v cc or gnd, i out = 0 5.5 3 a i cc increase in i cc per input one input at 3.4 v, other inputs at v cc or gnd 5.5 2.5 ma *typical values are at v cc = 5.0 v and t a = 25 c. 6. measured by the voltage drop between a and b pins at the indicated current through the switch. ac electrical characteristics limits t a = 40 c to 85 c v cc = 4.5 to 5.5 v v cc = 4.0 v symbol parameter conditions figures min max min max unit t phl , t plh prop delay bus to bus (note 7) v i = open 4 and 5 0.25 0.25 ns t pzh , t pzl output enable time v i = 7 v for t pzl v i = open for t pzh 4 and 5 1.0 5.0 5.5 ns t phz , t plz output disable time v i = 7 v for t plz v i = open for t phz 4 and 5 1.5 5.3 5.6 ns 7. this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc d elay of the typical on resistance of the switch and the 50 pf load capacitance, when driven by an ideal voltage source (zero output impedan ce). capacitance (note 8) symbol parameter conditions typ max unit c in control pin input capacitance v cc = 5.0 v 3 pf c i/o input/output capacitance v cc , oe = 5.0 v 5 pf 8. t a = 25 c, f = 1 mhz, capacitance is characterized but not tested.
74FST3125 http://onsemi.com 5 v i v ol v ol + 0.3 v t plh t plh vmi v ol v oh v oh ? 0.3 v t phzl t f = 2.5 ns 90 % 1.5 v 10 % 10 % 1.5 v 90 % t f = 2.5 ns t pzl t pzl output 1.5 v output 1.5 v gnd 3.0 v t pzh enable input t f = 2.5 ns 90 % 1.5 v 1.5 v 90 % 10 % 10 % 1.5 v 1.5 v v oh gnd 3.0 v switch input t f = 2.5 ns c l * from output under test figure 4. ac test circuit figure 5. propagation delays ac loading and waveforms notes: 1. input driven by 50 source terminated in 50 . 2. cl includes load and stray capacitance. *c l = 50 pf 500 500 figure 6. enable/disable delays output
74FST3125 http://onsemi.com 6 package dimensions soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 tssop?14 dt suffix case 948g?01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ?u? seating plane 0.10 (0.004) ?t? ??? ??? ??? section n-n detail e j j1 k k1 detail e f m -w- 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ?v? 14x ref k n n
74FST3125 http://onsemi.com 7 package dimensions qsop?16 qs suffix case 492?01 issue o min millimeters g r ?b? ?a? l m 0.25 (0.010) t u ?t? seating plane k d 16 pl c m 0.25 (0.010) t ba s s v n j m f 8 pl detail e detail e h x 45 rad. mold pin dim max min max inches a 4.80 4.98 0.189 0.196 b 3.81 3.99 0.150 0.157 c 1.55 1.73 0.061 0.068 d 0.20 0.31 0.008 0.012 f 0.41 0.89 0.016 0.035 g 0.64 bsc 0.025 bsc h 0.20 0.46 0.008 0.018 j 0.249 0.191 0.0098 0.0075 k 0.10 0.25 0.004 0.010 l 5.84 6.20 0.230 0.244 m 0 8 0 8 n 0 7 0 7 p 0.18 0.28 0.007 0.011 q 0.51 dia 0.020 dia r 0.64 0.89 0.025 0.035 u 0.64 0.89 0.025 0.035 v notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. the bottom package shall be bigger than the top package by 4 mils (note: lead side only). bottom package dimension shall follow the dimension stated in this drawing. 4. plastic dimensions does not include mold flash or protrusions. mold flash or protrusions shall not exceed 6 mils per side. 5. bottom ejector pin will include the country of origin (coo) and mold cavity i.d. 0 8 0 8 mark q p 0.013 x 0.005 dp. max rad. 0.005?0.010 typ
74FST3125 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 74FST3125/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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